Three-Dimensional Stateful Material Implication Logic

Monolithic three-dimensional integration of memory and logic circuits could dramatically improve performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metaloxide resistive switching devices (“memristors”), yet integration of logic circuits proves to be much more challenging. Here we demonstrate memory and logic functionality in a monolithic three-dimensional circuit by adapting recently proposed memristor-based stateful material implication logic. Though such logic has been already implemented with a variety of memory devices, prohibitively large device variability in the most prospective memristor-based circuits has limited experimental demonstrations to simple gates and just a few cycles of operations. By developing a low-temperature, low-variability fabrication process, and modifying the original circuit to increase its robustness to device imperfections, we experimentally show, for the first time, reliable multi-cycle multi-gate material implication logic operation within a three-dimensional stack of monolithically integrated memristors. The direct data manipulation in three dimensions enables extremely compact and high-throughput logic-in-memory computing and, remarkably, presents a viable solution for the Feynman’s grand challenge of implementing an 8-bit adder at the nanoscale. 1 Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106. Department of Material Science, University of California at Santa Barbara, Santa Barbara, CA 93106. Correspondence and requests for materials should be addressed to G. C. A. and D. B. S. (email: [email protected], [email protected] ). “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 2 of 14 Material implication (IMP) is a universal Boolean logic (Fig. 1a) particularly suitable for implementing “stateful” logic circuits. At the core of stateful logic are memory devices which serve a dual role performing computation and storing (latching) the results. The most prospective implementation is based on highly-scalable memristors. In the simplest case, memristors are two-terminal devices, whose conductance can be switched reversibly with relatively large (write) voltages, e.g. applying V  Vset to switch device to the ON state characterized by high conductance GON, and V Vreset to switch it to the OFF state with low conductance GOFF (Fig. 1b). The device’s conductance remains unchanged when relatively small (read) voltages are applied. Specifically, in one realization of memristor-based IMP logic, logic states ‘0’ and ‘1’ are encoded with low and high conductive states of a memristor. Using a divider circuits shown in Fig. 1c, q’ p IMP q, that is an implication between logic variables q and p, stored in memristors Q and P, respectively, is performed by applying specific “clock” voltage pulses VP and VL, so that the result of the computation is placed in Q as a new conductive state. Similar to other nonconventional computing approaches, voltage pulses VP and VL are effectively clock signals which do not carry any information. Their amplitudes are fixed and are chosen according to the load conductance GL, and memristor parameters, e.g. GON, GOFF, Vset, and Vreset for the ideal memristor without variations (Fig. 1b), such that the device Q switches from high to low conductive state only when device P is in the low conductive state. The appealing feature of stateful logic is that the result of the logic operation is immediately latched. Thus, IMP logic circuits based on non-volatile memristors are immune to shortages in power supply, which could be advantageous in the context of energy scavenging applications. Even more importantly, stateful logic does not draw static power and enables very high throughput information processing due to the possibility of fine-grained pipelining. In many respects, stateful IMP logic is similar to other logic-in-memory computing approaches, 20 which does not suffer from the memory bottleneck problem of conventional Von Neumann architectures. Several theoretical studies have predicted significantly higher performance and energy-efficiency for memristor-based IMP logic circuits and very similar concepts over conventional approaches for high-throughput computing applications. However, even simple experimental demonstrations of memristor-based IMP logic are challenging due to a memristor’s cycle-to-cycle and device-to-device variations. Device variations reduce allowed range of VP and VL voltages within which correct operation is “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 3 of 14 assured. In fact, IMP logic is more prone to variations and demonstration of memory functionality does not guarantee that the same circuit can be adapted for performing logic operations (Sec. 3 of Supplementary Information). Extending IMP logic to three dimensional circuits is even more difficult, demanding more sophisticated fabrication processes and higher integration density which can aggravate the device variation problems. The main goal of this paper is to address these challenges and ultimately demonstrate robust stateful IMP logic in monolithic three-dimensional metal-oxide memristor structures. The fabricated circuit consists of a two-level stack with four metal-oxide memristors. Two memristors were fabricated in the bottom level, and two others were monolithically integrated directly above, with all devices sharing a common middle electrode (Fig. 2a-c). The major steps involved in fabrication were: patterning of Ta/Pt bottom electrode by e-beam evaporation and lift-off; patterning of bottom device’s Al2O3/TiO2-x layer and Ti/Pt middle electrode by reactive sputtering and lift-off; planarization by chemical mechanical polishing and etch-back of plasma-deposited sacrificial silicon oxide; and, patterning of top device’s Al2O3/TiO2-x layer and Ti/Pt top electrode by reactive sputtering and lift-off (Fig. 2d-g). The device structure, oxide film thicknesses, and titanium oxide stoichiometry, which was controlled by changing oxygen to nitrogen flow ratio during sputtering, were selected based on our earlier study, with the primary objective of lowering forming voltages and improving uniformity of switching characteristics. In particular, thin Ti and Ta layers were deposited to improve electrode adhesion. Addition of Ti to the middle and top electrodes also ensured ohmic interfaces with the titanium dioxide layer, which was important for the device’s asymmetry. Low forming voltages reduced electrical stress during electroforming, while in-situ contacts between titanium oxide and the metal electrodes, which were fabricated without breaking the vacuum, ensured highquality interfaces, with both factors essential for improving uniformity of memristor’s switching characteristics. Furthermore, planarization reduced middle electrode roughness that resulted from residual sidewall deposition and was critical for lowering variations in top-level devices (Fig. S1-S3). The absence of annealing step, which is typically used for fine-tuning of the defect profile in metal oxide memristors, 24,28 and the low-temperature fabrication budget with temperatures below 300oC during the sputter deposition, simplified three-dimensional integration and makes the fabrication process compatible with conventional semiconductor “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 4 of 14 technology. More details on fabrication are provided in Section 1 of Supplementary Information. Figure 3a,b shows typical memristor I-V characteristics obtained by applying positive and negative quasi-DC triangular voltage sweeps. Switching polarities for all devices correspond to the bottom active interface, which is in agreement with the devices’ asymmetric structure. For all devices, the set switching is rather sharp, while the reset process is gradual. For example, for the device B1 reset transition starts at Vreset min ≈ -1.5 V; however, to avoid partial switching, voltage exceeding Vreset ≈ -2.2 V must be applied (Fig. 3b). A slightly thicker titanium dioxide layer for the bottom devices resulted in higher set threshold voltages as compared to those of the top ones (Figs. 3a and S4). As Figures 3c and d show, repetitive switching between ON and OFF states of one device did not disturb the state of others, thus suggesting that thermal crosstalk is negligible. Ratio of currents measured at 0.1 V between the ON and OFF states were well above one order of magnitude for all memristors. Other characteristics, such as endurance and retention, were close to those reported earlier for similar devices. Significant set threshold voltage variations (Fig. 3b) is a major challenge for implementing IMP logic. Therefore, it is natural to choose circuit parameters (i.e. GL, VL, VP) that maximize the range of variations, also referred as margins, which can be tolerated without comprising the correctness of logic operation. Some earlier works suggested choosing GL‘ = (GONGOFF ) 1/2 for the most optimal design, however, our simple analysis of IMP logic operation (Sec. 3 of Supplementary Information) shows that set margins monotonically increase as the load conductance decreases (Fig. 1e, f). The largest margins are for GL = 0, which cannot be implemented with the original circuit, though can be easily realized by replacing the load resistance and voltage source with a current source (Fig. 1d). The transition from the original circuit with earlier suggested GL‘ to the modified one with an optimized current source IL increased set margins by more than 20% (Fig. 1e). Such a boost in variation tolerance was critical for our experiment by allowing it to cope with virtually all experimentally observed variations (Fig. S5). It should be noted that, in principle, IMP logic can also be implemented using a memristor’s reset transition, i.e. assuming that logic states “0” and “1” are represented by the ON and OFF states instead. However, this would not be helpful in our case, because of the gradual reset transition– see Section 3 of Supplementary Information for more details. “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 5 of 14 Using the variation tolerant design with optimal values of IL and VP, which were obtained from accurate numerical simulations based on experimental (nonlinear) I-V curves, we successfully demonstrated IMP logic with the fabricated memristor circuit (Figs. 4 and 5). In the first set of experiments, a series of IMP operations were performed sequentially utilizing four different pairs of memristors (Figs. 4 and S7). Before each logic operation, the devices were always written to the specified initial states, therefore this experiment is a proof of memory and logic functionality implemented within the same circuit. Moreover, the considered pairs constitute all possible combinations of memristor’s polarities in IMP circuit and hence are sufficient to compute and move information in any direction within the circuit. In most cases of the first experiment, output conductances are close to the extreme ON and OFF values, so that it should be possible to cascade IMP logic gates, i.e. use the output of one gate as an input for the other. To confirm this, in the next series of experiments, we implemented NAND Boolean logic operation, for which inputs were the states of the bottom level devices and the output was stored in one of the top level memristors (Fig. 5). The NAND gate was realized in three steps an unconditional reset, followed by two sequential IMP operations. The result of the first IMP operation was stored in the top level device, which was then used as one of the inputs to the second IMP gate. In some rare cases (~ 6.5% of total IMP operations), there is some visible reduction in the ON-to-OFF conductance ratio. This is not desirable because set margins decrease with ON-to-OFF ratio (Fig. 1e). One plausible solution to restore the ratio is to read the state and write it back, i.e. similar to what was implemented in the first experiment. Interestingly, three-dimensional IMP logic enables a practical solution for one of the Feynman Grand Challenges – the implementation of an 8-bit adder which fits in a cube no larger than 50 nanometres in any dimension. The major building block – a full adder, which adds Boolean variables a, b, and cin to calculate sum s, and carry-out cout, requires 6 memristors and consists of two monolithically stacked 2×2 crossbars sharing the middle electrodes (Fig. 6a). Two of the memristors in the crossbar are assumed to be either not formed or always kept in the OFF state (Fig. 6b), which eliminates leakage currents typical for crossbar circuits and makes IMP logic set margins similar to those of the demonstrated circuit. In particular, at the start of computation, a, b, and cin are written to the specific locations in the circuit (Fig. 6c). A sequence of NAND operations, each consisting of one unconditional reset step and two IMPs (Fig. 5), is then performed to compute cout and s according to the particular implementation of “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 6 of 14 Fig. 6d. An occasional NOT operation is implemented with one unconditional reset step and one IMP step and is used to move variables within the circuit. In total, the full adder is implemented with 9 NAND gates and 4 NOT gates, i.e. 13 unconditional reset steps and 22 IMP steps. The simplest way to read an output of an adder is to measure electrically the state of memristors T2 and T3 (Fig. 6c). Alternatively, the output can be sensed as a mechanical deformation of upper metal electrodes, which is often observed in metal-oxide memristors, or using scanning Joule expansion microscopy. Finally, a full 8-bit adder could be implemented in a ripple-carry style by performing full adder operation 8 times. In summary, we have demonstrated logic-in-memory computing in three-dimensional monolithically integrated circuits. As the memristor technology continues its rapid progress and will eventually become sufficiently advanced to enable large-scale integration of memristive devices with sub-nanosecond, pico-Joule switching with >10 cycles of endurance, which so far was demonstrated for discrete devices, we expect that the presented approach will become attractive for high-throughput and memory-bound computing applications suffering from memory bottleneck problems. Furthermore, we showed how the presented approach establishes a realistic pathway towards resolving one of the Feynman’s Grand Challenges. The remaining challenge is to scale down the circuitry (Fig. 6a), which does not seem unrealistic task given that discrete metal-oxide memristors with similar dimensions and much more complex (but less dense) memristive circuits have been already demonstrated. 4,5,7,28 Acknowledgments We acknowledge useful discussions with F. Alibart, F. Merrikh-Bayat, B. Mitchell, J. Rode, and B. Thibeault. This work was supported by the AFOSR under the MURI grant FA9550-12-1-0038, by DARPA under Contract No. HR0011-13-C-0051UPSIDE via BAE Systems, and by the Department of State under the International Fulbright Science and Technology Award. Author Contributions G.C.A., B.D.H., and D.B.S. designed research. G.C.A. and B.D.H. performed fabrication, device characterization, and circuit experiments. M.P. advised on the device fabrication. D.B.S. advised on all parts of the project. All discussed and interpreted results. G.C.A. and D.B.S. wrote the manuscript. “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 7 of 14 References 1. Topol, A. W. et al. Three-dimensional integrated circuits. IBM J. Res. Develop. 50, 491506 (2006). 2. Xie, Y., Loh, G. H., Black, B. & Bernstein, K. Design space exploration for 3D architectures. ACM JETC 2, 65-103 (2006). 3. KT Park et al. Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming. IEEE J. Solid-State Circuits 50, 204-213 (2015). 4. Parkin, S. S. P., Hayashi, M., & Thomas, L. Magnetic domain-wall racetrack memory. Science 320, 190-194 (2008). 5. Chevallier, C. J. et al. 0.13 μm 64 Mb multi-layered conductive metal-oxide memory. ISSCC’10, 260-261 (2010). 6. Kawahara, A. et al. An 8 Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput. ISSCC’12, 432-434 (2012). 7. Yu, S. et al. HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. ACS Nano 7, 2320-2325 (2013). 8. Liu, T. et al. A 130.7-mm 2-layer 32-Gb ReRAM memory device in 24-nm technology. IEEE J. Solid-State Circuits 49, 140-13 (2014). 9. Ahn, J. H. et al. Heterogeneous three-dimensional electronics by use of printed semiconductor nanomaterials. Science 314, 1754-1757 (2006). 10. Lavrijsen, M. R. et al. Magnetic ratchet for three-dimensional spintronic memory and logic. Nature 493, 647-650 (2013). 11. Borghetti, J. et al. ‘Memristive’switches enable ‘stateful’ logic operations via material implication. Nature 464, 873-876 (2010). 12. Xianwen, S. et al. Unipolar memristors enable “stateful” logic operations via material implication. Appl. Phys. Lett. 99, 072101 (2011). 13. Prezioso, M. et al. A single‐device universal logic gate based on a magnetically enhanced memristor. Adv. Mater. 25, 534-538 (2013). 14. Elstner, M. et al. Molecular logic with a saccharide probe on the few-molecules level. J. Am. Chem. Soc. 134, 8098-8100 (2012). “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 8 of 14 15. Mahmoudi, H. et al. Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory. Solid-State Electronics 84, 191-197 (2013). 16. Siemon, A. et al. Realization of Boolean logic functionality using redox-based memristive devices. Adv. Funct. Mat. (2015) advanced publication. 17. Likharev, K. K. & Korotkov, A. N. Single-electron parametron: Reversible computation in a discrete state system. Science 273, 763-76 (1996). 18. Cowburn, R. P. & Welland, M. E. Room temperature magnetic quantum cellular automata. Science 287, 1466-1468 (2000). 19. Behin-Aein, B., Datta, D., Salahuddin, S. & Datta, S. Proposal for an all-spin logic device with built-in memory. Nature Nanotech. 5, 266-270 (2010). 20. Di Ventra, M. & Pershin, Y. V. The parallel approach. Nature Physics 9, 200-202 (2014). 21. Feynman Grand Prize, full description available online at https://www.foresight.org/GrandPrize.1.html 22. Yang, J., Strukov, D. B. & Stewart, D. R. Memristive devices for computing. Nature Nanotechnology 8, 13-24 (2013). 23. Wong, H.-S. P. & Salahuddin, S. Memory leads the way to better computing. Nature Nanotechnology 10, 191-194 (2015). 24. Govoreanu, B. et al. Vacancy-modulated conductive oxide resistive RAM (VMCORRAM). IEDM Tech Dig., 10.2.1 10.2.4 (2013). 25. Wulf, W. A. & McKee, S. A. Hitting the memory wall: implications of the obvious. ACM/SIGARCH Computer Architecture News 23, 20-24 (1995). 26. Mane, P. et al. Stateful-NOR based reconfigurable architecture for logic implementation. Microelectronic J. 46, 551-562 (2015). 27. Hamdioui, S. et al. Memristor based computation-in-memory architecture for dataintensive application, DATE’15, 1718-1725 (2015). 28. Prezioso, M. et al. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521, 61-64 (2015). 29. Yang, J. J. et al. Memristive switching mechanism for metal/oxide/metal nanodevices. Nature Nanotechnology 3, 429-433 (2008). 30. Mikheev, E., Hoskins, B. D., Strukov, D. B. & Stemmer, S. Resistive switching and its suppression in Pt/Nb: SrTiO3 junctions, Nature Communications 5, 3990 (2014). 31. Lehtonen, E., Poikonen, J. H., & Laiho, M. Memristor Networks. (Adamatzky, A. & Chua, L. ed.) 603 (Springer International Publishing, Switzerland, 2014). “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 9 of 14 32. Yang, J. J. et al. The mechanism of electroforming of metal oxide memristive switches. Nanotechnology 20, 215201 (2009). 33. Varesi, J. & Majumdar, A. Scanning Joule Expansion Microscopy at nanometer scales, Applied Physics Letters 72, 37 (1998). 32. Parhami, B. Computer arithmetic: Algorithms and hardware designs. (Oxford University Press, Inc., New York, NY, 2009). “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 10 of 14 Figure captions Figure 1. Memristor-based material implication logic: (a) Logic truth table and its mapping to memristor’s states. (b) A sketch of simplified (linear) I-V switching curve for a memristor. The thick (thin) solid lines show schematically an I-V curve with average (maximum and minimum) set and reset thresholds. The inset shows experimental setup. (c) Originally proposed and (d) modified IMP logic circuits with particular polarity of memristors. (Other possible configurations are shown in Fig. S6.) (e) The set margins as a function of load conductance for several representative ON-to-OFF conductance ratios. For convenience, margins and load conductances are normalized with respect to mid-range set voltages Vset and GON, respectively. Solid dots show margins for previously proposed optimal load conductance GL’, while solid triangles are margins which were obtained with numerical simulations using experimental device characteristics. The solid and dashed horizontal lines denote the maximum and the actual set margins, respectively, when taking into account experimental data. (f) A diagram showing definition of margins in the context of set transition. Figure 2. The Al2O3/TiO2-x memristor circuit: fabrication details. (a) An equivalent circuit. B1 and B2 denote bottom devices, while T1 and T2 the top ones. (b) A cartoon of device’s cross-section showing the material layers and their corresponding thicknesses. (c) A top-view scanning-electron-microscope image of the circuit. The red, blue, and purple colours were added to highlight the location of bottom and top devices, and their overlap, respectively. (de) A top-view atomic-force-microscope images of the circuit during different stages of fabrication, in particular showing: (d) bottom electrode; (e) middle electrode; (f) middle electrode after planarization step; and (g) top electrode. Figure 3. The Al2O3/TiO2-x memristor circuit: electrical characterization. (a) Representative IV curves for all devices. (b) Switching I-Vs showing 100 cycles of operation for the device B2 and the corresponding cycle-to-cycle set switching voltage statistics. (c) Conductance of the device B1 that was repeatedly switched 200 times and (d) those of the other three devices in the circuit that were kept in the OFF states for the first 100 cycles, and then in the ON states for the remaining 100 cycles. In all experiments, the memristors were switched by applying triangular voltage pulses to the corresponding top terminal of the device. Figure 4. Material implication logic results. (a-d) Circuit schematics, and (e-i) corresponding experimental results showing device’s conductances before and after IMP operation “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 11 of 14 implemented with various initial states and pairs of memristors in a circuit. On panels (e-i) each graph shows the averaged conductances and their standard deviations for 20 experiments. IMP logic was performed by biasing device VP = 0.25 V and applying a 10-ms IL = 550 μA load current pulse for the cases on panels (a, d), i.e. when the result was written into the bottom device, and IL = 200 μA when the output was one of the top devices (panels b, c). Figure 5. NAND Boolean operation via material implication logic. (a) Schematics and truth table showing intermediate steps. (b) Experimental results showing 80 cycles of operation with >93% yield for all four combinations of initial states. The initial states were set similarly to the Figure 4 experiments, while VP = 0.15 V, and load current was applied as 10-ms pulse with IL = -550 μA. Figure 6. A full adder implementation with 3D IMP logic: (a) Cartoon of a structure and (b) its equivalent circuit. (c, d) A sequence of steps and specific mapping of logic variables to the circuit’s memristors for a particular implementations of full adder shown on panel d. The last step on panel d, in which cout is placed in the same location as cin, is only required to ensure modular design, but might be omitted in more optimal implementations. “Three-Dimensional Stateful Material Implication Logic” by Adam et al., Sept. 2015 Page 12 of 14 Figure 1